Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading a test pattern or stimulus into scanable memory elements of the system, capturing the response of the elements to the test stimulus, shifting the test response out of the system and then comparing the response to the response which should have been obtained if the system was operating according to design. Difficulties arise when signals cross the boundary between clock domains having different clock frequencies. Since the elements in one domain operate at a different frequency from that of other domains in the system, special provisions must be made during testing to ensure that signals traversing clock domains are synchronized. Otherwise, the test response from the system will not be repeatable and test results will be unreliable. The problem is especially severe in built-in self-test systems.
Methods have been developed for testing systems in which the ratio of the frequencies of two clock domains is an integer. However, it is not uncommon for digital systems to employ asynchronous clocks whose frequencies are not multiples of each other. For example, one clock domain could employ a clock rate of 200 MHz and other domain could employ a clock rate of 78 MHz, resulting in a non-integer frequency ratio of 2.564 . . . Solutions have yet to be developed for clock domains having non-integer frequency ratios. Testing of such systems using the functional system clocks is difficult because the phase relationship between the system clocks is not known and is variable over time. The term "functional system clock" refers to the normal operating frequency of a digital system or portion thereof. In order to achieve very high reliability circuits, it is essential that all clock domains be tested at full-speed.
Heretofore, such circuits have been tested by using test clock rates that are essentially the same as the functional clock rates but disabling all signal paths crossing clock domain boundaries and repeating the test for each clock domain. The primary drawbacks of this approach are that part of the logic is not tested and a series of tests must be performed in order to test all parts of the system. However, even then, it is not possible to obtain results for all parts of the system operating concurrently at speed.
It is also known to use test clock rates that are as close as possible to those of the functional clocks without exceeding the functional clock rates and that are multiples of each other. This is done by using the fastest functional clock as the test clock for the domain with the fastest clock rate and generating the test clocks required by other clock domains from the main test clock signal using a simple clock divider. For example, in a system having one clock domain with a functional clock frequency of 200 MHz and another clock domain with a clock frequency of 78 MHz, test clock rates of 200 MHz and 50 MHz would be used for testing. Nadeau-Dostie et al U.S. Pat. No. 5,349,587 granted on Sep. 20, 1994 for "Multiple Clock Rate Test Apparatus for Testing Digital Systems" and Bhawmik U.S. Pat. No 5,680,543 granted on Oct. 21, 1997 for "Method and Apparatus for Built-In Self-Test With Multiple Clock Circuits" illustrate the latter approach. Clearly, the primary drawback of this approach is that one of the clock domains is not tested at its full-speed (78 MHz).
It is also possible to combine the above methods sequentially. The drawbacks of this approach are longer test times, more complex test circuitry than is desirable and the inability of simultaneously or concurrently testing all components at their functional clock rates.
Thus, there is a need for testing method and circuitry which enables the testing at the design or functional speed of digital systems having two or more clock domains with asynchronous clocks whose frequencies are not multiples of one another.